Integrated circuit (IC) dice tend to be fragile and are typically packaged for protection from physical damage and for heat dissipation. ICs may comprise one or more passive and/or active elements, one or more layers of metal interconnects and one or more layers of dielectric material. The dielectric layer formed between metal interconnects may be referred to as “inner layer dielectric” (ILD). An IC die and package are typically electrically interconnected via a first level interconnect (FLI) such as, for instance, by wirebonding or soldering.
During package assembly an IC die and package may be exposed to repeated thermal cycles which may induce thermomechanical stress on the ILD and solder joints. For instance, package assembly may include die placement at room temperature, solder reflow in the range of 220 degrees Celsius (° C.), cooling again to room temperature, deflux performed in the range of 90° C., prebake performed in the range of 160° C., underfill dispense performed in the range of 110° C., cooling again to room temperature and then underfill cure performed in the range of 160° C.
Other factors in the packaging process may cause additional temperature fluctuations. For instance, various stages of the assembly process take place in different pieces of assembly equipment. While being transferred on the line or off the line from one assembly apparatus to another, an IC/package assembly may cool significantly. Also, there may be downtime on the line caused by underfill bottlenecking, assist or material replenishment or lot changeover. In the event of downtime on the line, an IC/package assembly may cool while waiting for the line to return to function. Multiple thermal cycles with temperature fluctuations ranging to about 200° C. may have deleterious effects on ILD and solder joints due in part to coefficient of thermal expansion (CTE) mismatch between the IC and the package substrate.
Thermomechanical stresses during packaging may exceed the effective strength of ILD and solder joints which may result in ILD and solder joint cracking. Such defects may cause IC failures. Further, due to a constant drive to reduce die size and improve performance, FLI solder bump pitches and diameters are decreasing. To improve electrical performance, manufacturers are increasingly using low dielectric constant (low k) materials in ICs which tend to be weaker than previously used ILD materials. Both trends may further reduce solder joint and underlying ILD strength increasing the damaging effects of CTE mismatch during packaging.